1. Field of the Invention
The present invention relates to a data processing apparatus with a cache memory (for example, a microprocessor), in particular, to a data processing apparatus with a cache controlling device that causes either of a data write request sent from a cache write buffer to a cache memory or a data read request sent from the cache memory to have precedence over the other, according to various conditions.
2. Description of the Related Art
FIG. 1 is a block diagram showing the configuration of a conventional cache block and a conventional CPU block. In FIG. 1, the cache block comprises a data cache storing device 1, a data cache controlling device 2 that controls data input and data output to and from the data cache storing device 1, and a cache write buffer 3 that temporarily stores data to be written to the data cache storing device 1. The CPU block comprises an instruction controlling device 4 that outputs, for example, a load/store instruction to the data cache controlling device 2, an arithmetic processing device 5 that performs various arithmetic operations, and a register file 6 that stores arithmetic operation data and so forth.
In FIG. 1, when the CPU block detects the load/store instruction, the CPU block causes the data cache controlling device 2 to execute the instruction. The arithmetic processing device 5 calculates a cache access address (data address). The cache access address is supplied to the data cache controlling device 2 and the data cache storing device 1. When the load instruction is detected, after it is determined whether or not a cache hit takes place, the load data is output from the data cache storing device 1 to the register file 6. When the store instruction is detected, store data is temporarily written from the register file 6 to the cache write buffer 3. A data storage request is output from the cache write buffer 3 to the data cache controlling device 2. In accordance with the data storage request the data cache controlling device 2 causes the data cache storing device 1 to store the swore data of the cache write buffer 3.
FIG. 2 is an operation time chart showing the execution of the load instruction shown in FIG. 1. In FIG. 2, when the data cache controlling device 2 receives the load instruction along with the data address at cycle T1, it accesses the cache memory at cycle T2. The data cache storing device 1 comprises a cache tag that stores a line address of the cache memory and a random access memory (RAM) portion. At cycle T2, both the cache tag and the RAM are accessed. At cycle T3, it is determined whether or not the read request data is stored in the cache (namely, a cache test takes place). When a cache hit is determined, the load data that is read from the cache memory is sent to the register file 6.
FIG. 3 is an operation time chart of the store instruction shown in FIG. 1. In FIG. 3, when the data cache controlling device 2 receives the store instruction along with the data address at cycle T1, as with the case of the load instruction shown in FIG. 2, the cache memory is accessed at cycle T2. At cycle T3, it is determined whether or not a cache hit takes place. When the store instruction is an instruction that causes data stored in the data cache storing device 1 to be rewritten, it is determined that a cache hit takes place. As shown in FIG. 1, the store data is stored in the cache write buffer 3 at cycle T4.
The store data stored in the cache write buffer 3 is stored in the data cache storing device 1 with precedence over, another instruction, for example, the load instruction. Alternatively, the store data is stored at a cycle at which another instruction such as the load instruction is not executed. In this case, the storage request of the store data that is output from the cache write buffer 3 is sent to the data cache controlling device 2. Corresponding to the storage request, the data cache controlling device 2 causes the data cache storing device 1 to store the store data. Since data to be stored in the cache is stored in the cache write buffer 3 at cycle T4, the cache storage request is sent to the data cache controlling device 2. When there is no instruction to be executed next, the storage data is stored in the data cache storing device 1 at cycle T5.
FIG. 4 is an operation time chart in the case that the data storage request that is sent from the cache write buffer3 to the data cache storing device 1 corresponding to the store instruction shown in FIG. 3, and the load instruction that causes data to be read from the data cache controlling device 2, contend. In FIG. 4, the operation will be described with an assumption that the store instruction has precedence over the load instruction. The, operations at cycles T1 to T3 of FIG. 4 are the same as those of FIG. 3. In FIG. 4, at cycle T4, the load instruction is supplied to the data cache controlling device 2 along with the data address.
In other words, at cycle T4, the cache storage request from the cache write buffer 3 and the load instruction contend. In this case, since the store instruction has precedence over the load instruction, the load instruction is not received at this cycle. Thus, data is stored from the cache write buffer 3 to the data cache storing device 1. Consequently, the load instruction is not received until the next cycle (cycle T5). At cycle T5, an instruction response that represents that the load instruction can be received is sent to the instruction controlling device 4. At cycle T6, the cache memory is accessed. At T7, when a cache hit is determined, the load data is output to the register file 6.
FIG. 5 is an operation time chart in the case that the store instruction and the load instruction contend. In this case, the load instruction has precedence over the store instruction. The operations at cycles T1 to T3 shown in FIG. 5 are the same as those shown in FIG. 3 as with the case shown in FIG. 4. At cycle T4, the load instruction and the data address are supplied to the data cache controlling device 2. Thus, the load instruction and the cache storage request contend. In this case, the load instruction has precedence over the cache storage request. Thus, at cycle T4, the instruction response is sent to the instruction controlling device 4. At cycle T5, the cache memory is accessed. At cycle T6, a cache hit is determined. The load data is output to the register file 6. The cache storage request sent from the cache write buffer 3 at cycle T4 is received by the data cache controlling device 2 at cycle T5. Thus, a cache storage response is output. At cycle T6, the store data is stored in RAM of the data cache storing device 1.
As described in FIG. 5, if the load instruction has precedence over the other instruction, after the load instruction is received and the signal level of the instruction response to the load instruction becomes xe2x80x9cLxe2x80x9d, the store data is sent from the cache write buffer to the data cache storing device. If the load instruction is cancelled, the store data cannot be sent from the cache write buffer to the data cache storing device.
FIG. 6 is a time chart for explaining such a problem. In FIG. 6, as with the case shown in FIG. 5, the load instruction and the cache storage request contend at cycle T4. When the load instruction has precedence over the other instruction, the store data is not stored in the cache memory at cycle T4. At cycle T5, the load instruction cancellation signal is sent from the instruction controlling device 4 to the data cache controlling device 2. This cancellation signal is sent from the instruction controlling device 4 to the data cache controlling device 2 in the case, for example, when the execution of an instruction of the CPU is stopped due to a particular cause. Next, the instruction cancellation signal will be described with reference to FIG. 7.
In FIG. 7, it is assumed that a pipeline of the instruction controlling device is composed of three stages that are a decode stage (D) in which an instruction is decoded, an execution stage (E) in which an instruction is executes, and a write stage (W) in which the execution result is written. If the execution stage is interlocked due to a particular cause after the decode stage of the pipeline, the cache controlling device executes a pipeline composed of three stages that are a priority check P corresponding to the E stage of the instruction, a tag determination T, and a cache hit determination C, after an instruction is issued from the instruction controlling device. When the E stage is interlocked three times in the instruction controlling device, a priority check stage of a pipeline (1) and a tag determining stage and a hit determining stage of a pipeline (4) become valid. The operations from a tag determining stage of the pipeline (1) to a priority check stage of the pipeline (4) are cancelled.
In FIG. 6, the load instruction cancellation signal is sent to the data cache controlling device 2 at cycle T5. While the load instruction cancellation signal is being issued, the store data stored in the cache write buffer 3 is not sent to the data cache storing device 1. In other words, the load instruction supplied from the instruction controlling device 4 at cycle T4 is cancelled at cycle T5. However, since the load instruction still maintains the access right to the data cache storing device 1, the store data to be sent to the cache write buffer 3 is not sent to the cache memory due to the invalid load instruction.
When the load instruction to be cancelled and the stored instruction contend, the period during which the store instruction and the load instruction interfere with each other becomes long. In addition, depending on the canceling method, a serious problem may arise, that is, the system may not work properly.
An object of the present invention is to provide a data processing apparatus that allows data sent from a cache write buffer to a cache memory to have the precedence over another instruction, even if a store instruction sent from the cache write buffer to the cache memory and the other instruction such as a load instruction contend.
To accomplish such an object, the data processing apparatus according to the present invention comprises a cache store data storing portion (for example, a cache write buffer) and a cache controlling portion (for example, a data cache controlling device).
The cache store data storing portion temporarily stores store data to be stored in the cache storing device. When store data is supplied from, for example a register file, the data is written to the cache store data storing portion. Thereafter, a data storage request that is, for example a storage request low signal, is output from the cache store data storing portion to the cache controlling portion.
The cache controlling portion (for example, the data cache controlling device) executes one of a control operation that causes a data read request received from the cache storing device against, for example a load instruction, to have precedence over a data storage request that is output from, the cache store data storing portion for example, the cache write buffer, and a control operation that causes the data storage request to have precedence over the data read request when the data read request and the data storage request contend.
The cache store data storing portion comprises, for example, one or more cache write buffers and a cache write buffer controlling device that controls data input and data output to and from the cache write buffer. When data to be stored in the cache storing device is written to the one or more cache write buffers, the data storage request is output as, for example, a storage request low signal. The storage request low signal causes the data read request against the load instruction to have precedence over the storage of the data to the cache storing device against the storage request. When the storage request and the data read request against the load instruction contend, the data read process has the precedence over the storage request. The data storage against the storage request is executed after the signal level of the instruction response to the storage request becomes xe2x80x9cLxe2x80x9d.
According to the present invention, even if the store instruction and the load instruction contend and the load instruction has precedence over the store instruction, an instruction cancellation signal against the load instruction received from, for example the instruction controlling device, is input to the cache write buffer controlling device. Alternatively, an address conversion validity signal that is output from an address conversion controlling device is input to the cache write buffer controlling device. As a further alternative, after a predetermined number of cycles elapses after data is written to the cache write buffer, a storage request high signal instead of the storage request low signal is output from the cache write buffer controlling device to the cache controlling portion. The storage request high signal causes the data storage performed from the cache write buffer to the cache storing device to have the precedence over the data read process against the load instruction. The cache controlling portion causes the data storage process to have precedence over the other operation. Thus, data is stored in the cache storing device.
Consequently, even if the store instruction contends with the load instruction, the data storage process performed from the cache write buffer to the cache memory has the precedence over the other operation.
These and other object, features and advantages of the present invention will become more apparent in light of the following detailed description of a best mode embodiment thereof, as illustrated in the accompanying drawing.